On September 7, 2026, Huawei announced the Mate XT 2 triple-foldable phone in Guangzhou, equipped with the new generation Kirin 9050 Pro chip. This chip was released again after 6 years, utilizing innovative logic folding technology to stack digital, analog, and storage circuits vertically, and by adding vertical interconnect channels, the signal transmission path was shortened. Compared to the previous generation, performance improved by 42%, achieving a dual upgrade in both performance and energy efficiency. This breakthrough broke away from traditional planar design concepts and provided the domestic chip industry with a new approach to tapping performance potential through architectural reengineering, in addition to缩小 transistors. This achievement confirms the steady improvement in China’s upstream and downstream chip support and engineering capabilities, but the industry still faces challenges due to weak core components, and is in a critical phase of development.
Huawei released the Kirin 9050 Pro chip on September 7, 2026, in Guangzhou. Its performance is 42% better than that of the previous generation.
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2026-09-07
Huawei released the Kirin 9050 Pro chip
On September 7, Huawei announced the Mate XT 2 phone equipped with this chip in Guangzhou. The chip was released after 6 years and uses logical folding technology, achieving a 42% performance improvement compared to the previous generation.
On September 7, Huawei unveiled the Mate XT 2 three-foldable phone equipped with the Kirin 9050 Pro chip in Guangzhou. This is the first time in six years that Huawei has introduced a new Kirin chip since the Mate40 launch. The chip utilizes logical folding technology, stacking digital, analog, and storage circuits vertically, and by adding vertical interconnect channels, it shortens the signal transmission path, thereby reducing latency and improving performance. Previously, Huawei proposed a “logical folding” semiconductor design methodology aimed at reconstructing circuit layouts in three-dimensional space to achieve coordinated optimization of performance, power consumption, and area.