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Huawei releases latest paper data to address concerns about 3D stacking heat generation and announces actual performance and power consumption results of Kirin 2026.
He Tingbo, President of Huawei’s Semiconductor Business Unit, updated his paper “Will Huawei’s chips melt?” on September 4th, responding to industry doubts about the heat generated by 3D stacked chips with real-world data. Kirin 2026 uses “logical folding” technology, replacing horizontal wiring with vertical interconnects, shortening critical paths by two to seven times and increasing transistor density by 55% ( reaching 238 million per square millimeter). At the same performance level, the power consumption of NPU, GPU, and CPU drops by 66%, 58%, and 41%, respectively. When operating at full speed, the NPU’s computing power is increased by 141% compared to the previous generation. Huawei points out that heat is mainly caused by data transmission rather than computation itself, and local high heat issues are addressed by optimizing circuit layout and voltage frequency. Although the current hybrid bonding spacing is 1.5 micrometers, plans are to increase it to 720 nanometers or even 480 nanometers within the next three years, and to raise the CPU core frequency to above 5GHz. Analysts believe that the post-manufacturing testing equipment sector will benefit directly, but weaknesses such as EDA tools, operating system scheduling, and standard interfaces still need to be addressed…
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Huawei releases latest paper data to address concerns about 3D stacking heat generation and announces actual performance and power consumption results of Kirin 2026.
SSEEC Daily reports that He Tingbo updated his paper “Will Huawei’s Tao chip melt?” on September 4, presenting theoretical views and refining existing findings.
SSEEC Daily reports that the transistor density of Kirin 2026 has increased from 155 million to 238 million units, with the critical path shortened by 70%, based on logic folding technology.
Phoenix Network, SSEEC Daily, TechWeb report that He Tingbo updated his paper to address heat generation concerns, announcing a 55% increase in transistor density and 66%/58%/41% reductions in NPU/GPU/CPU power consumption.
3 reportsHe Tingbo, the head of Huawei's semiconductor department, updated the paper related to “Tao’s Law”. Written by He Tingbo, this paper aims to elaborate on his theoretical views in the field of semiconductors. This update serves as a supplement and refinement to the original research findings, reflecting Huawei’s continuous exploration in chip technology.
The transistor density of Huawei’s Kirin 2026 chip increased by 55% to 238 million per square millimeter. Under the same performance, the power consumption of the NPU, GPU, and CPU decreased by 66%, 58%, and 41%, respectively. This achievement is based on logic folding technology, which reduces the signal transmission distance through vertical circuit stacking, shortening the core wiring length by approximately 20% and reducing some critical paths by up to 70%. He Tingbo, head of Huawei’s semiconductor division, confirmed in the paper that the energy consumption mainly stems from data transmission rather than computation itself. The second-generation folding solution has solved the problem of increased power density. Over the next three years, Huawei plans to increase the hybrid bonding spacing to 720 nanometers and further reduce it to 480 nanometers, while also increasing the CPU core frequency to above 5GHz.
He Tingbo, President of Huawei’s Semiconductor Business Unit, recently published a paper in which he used actual production chip data to refute the industry claim that “3D stacking inevitably generates heat”. The Kirin 2026 chip, which uses logic folding technology, has a 55% increase in transistor density. Under the same performance conditions, the power consumption of NPU, GPU, and CPU cores decreases by 66%, 58%, and 41%, respectively. This chip uses vertical interconnects instead of horizontal traces to shorten the critical path length, reduce interconnection capacitance, lower the operating voltage, and optimize the layout strategy for thermal management. Kirin 2026 is the first mobile SoC to use logic folding; its performance improvement comes entirely from architectural changes rather than new lithography processes.
He Tingbo, head of Huawei's semiconductor division, updated his paper “Was Huawei's τ Chip Supposed to Melt?” on September 4, addressing concerns about heat generation in 3D stacked chips and presenting latest data. Tests show that the transistor density of Kirin 2026 has increased by 55% compared to Kirin 9030 Pro. The power consumption of the NPU, GPU, and CPU modules has decreased by 66%, 58%, and 41%, respectively, under the same performance conditions. Huawei stated that the heat is caused by data transmission rather than computing itself. The local high heat problem is solved by shortening wire lengths through circuit folding and reducing the operating voltage frequency of the core. Engineering challenges such as mixed bonding spacing and wafer warping still require efforts over the next three to five years. According to research reports from Guojin Securities and Kaiyuan Securities, post-processing testing equipment represents a more direct incremental direction for growth. Equipment segments such as Fab, CP testing, and new etching and thin-film deposition processes will benefit.
He Tingbo, President of Huawei’s Semiconductor Business, presented a paper in which he used actual measurement data from the Kirin 2026 chip to address concerns about three-dimensional stacking heat dissipation. The paper, titled “Will Huawei’s Tachyon Chip Meltdown?”, is the third publication of its kind within four months, following two previous versions. Through the “logical folding” technology, Kirin 2026 reduces NPU power consumption by 66% and GPU power consumption by 58% while maintaining the same AI inference performance; in contrast, DSP power density increases by 24%. At full speed, the NPU can achieve up to 70 TOPS, a 141% increase over previous generations. The team noted that this technology reduces the signal transmission distance by two to seven times, thereby cutting heat generation at the source. The roadmap for three-dimensional interconnection spacing shows that the current 1.5-micron bonding spacing will be reduced to 1 micron in the next-generation Kirin 2027. Tian Feng, Director of Kuaisi Manxi Research Institute, believes that interconnection precision has become a new key area of focus, but rewriting industry rules requires addressing shortcomings such as EDA tools, operating system scheduling, and standard interfaces.