The revised “Regulations on the Protection of Integrated Circuit Layout Design” issued by State Council Order No. 842 will come into effect on October 15, 2026. The new regulations expand the scope of protection to functional areas such as integrated optics and quantum technologies, and introduce a punitive compensation mechanism. For serious cases of intentional infringement, the compensation amount can be determined to be 1 to 5 times the original amount. Additionally, the regulations clarify the principle of good faith and rules for dealing with monopolies involving abuse of proprietary rights, and include provisions for reciprocal retaliation. The focus of the revision is to strengthen the protection of “layout design” at the intermediate level. It addresses common “soft copying” practices in the industry (i.e., fine-tuning geometric structures using EDA tools while maintaining equivalent circuit behavior), defines originality as those elements removed from conventional industry designs, and significantly lowers the tolerance threshold for similarity.
Beijing Intellectual Property CourtChina Semiconductor Industry AssociationDecree No. 842 of the State CouncilQorvoSkyworksUnisoc Sharp“Regulations on the Protection of Integrated Circuit Layout Design”
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Decree No. 842 of the State Council1
“Regulations on the Protection of Integrated Circuit Layout Design”1
Decree No. 842 of the State Council, the revised “Regulations on the Protection of Integrated Circuit Layout Designs”, came into effect on October 15. It has been 25 years since its first publication in 2001. The new regulations expand the scope of protection to integrated photons, quantum technologies, and other functions, and introduce a punitive compensation mechanism: for serious cases of intentional infringement, the compensation amount can be determined from 1 to 5 times the original amount; at the same time, the principle of good faith and handling of monopolies involving abuse of proprietary rights are clarified, and reciprocal retaliation clauses are added. The focus of the revision is to strengthen the protection of “layout designs” in intermediate layers. It targets common “soft plagiarism” practices in the industry (i.e., fine-tuning geometric structures using EDA tools while maintaining equivalent circuit behavior), defines originality as those excluded from conventional industry designs, and significantly reduces the tolerance threshold for similarity. In response to issues such as competition and low gross profit margins in fields like radio frequency frontends due to pin-to-pin compatibility, although these regulations cannot change the structural situation where interface standards are dominated by main chip platforms, they aim to provide negotiation advantages for small and medium-sized design companies by increasing the cost of infringement and the difficulty of providing evidence, thereby promoting layout registration from…